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this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. for further information contact your local stmicroelectronics sales office. april 2012 doc id 022985 rev 1 1/46 1 stm8l051f3 value line, 8-bit ultralow power mcu, 8-kb flash, 256-byte data eeprom, rtc, timers, usart, i2c, spi, adc data brief ? preliminary data features operating conditions ? operating power supply: 1.8 v to 3.6 v temperature range: ? 40 c to 85 c low power features ? 5 low power modes: wait, low power run, low power wait, active-halt with rtc, halt ? ultralow leakage per i/0: 50 na ? fast wakeup from halt: 5 s advanced stm8 core ? harvard architecture and 3-stage pipeline ? max freq: 16 mhz, 16 cisc mips peak ? up to 40 external interrupt sources reset and supply management ? low power, ultrasafe bor reset with 5 selectable thresholds ? ultra low power por/pdr ? programmable voltage detector (pvd) clock management ? 32 khz and 1 to 16 mhz crystal oscillators ? internal 16 mhz factory-trimmed rc ? internal 38 khz low consumption rc ? clock security system low power rtc ? bcd calendar with alarm interrupt ? digital calibration with +/- 0.5 ppm accuracy ? lse security system ? auto-wakeup from halt w/ periodic interrupt memories ? 8 kbytes of flash program memory and 256 bytes of data eeprom with ecc ? flexible write and read protection modes ? 1 kbyte of ram dma ? 4 channels supporting adc, spi, i2c, usart, timers ? 1 channel for memory-to-memory 12-bit adc up to 1 msps/28 channels ? internal reference voltage timers ? two 16-bit timers with 2 channels (used as ic, oc, pwm), quadrature encoder ? one 8-bit timer with 7-bit prescaler ? 2 watchdogs: 1 window, 1 independent ? beeper timer with 1, 2 or 4 khz frequencies communication interfaces ? synchronous serial interface (spi) ?fast i 2 c 400 khz smbus and pmbus ?usart up to 18 i/os, all mappab le on interrupt vectors development support ? fast on-chip programming and non- intrusive debugging with swim ? bootloader using usart table 1. device summary reference part number stm8l051xx stm8l051f3 tssop20 www.st.com
contents stm8l051f3 2/46 doc id 022985 rev 1 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 ultra low power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 central processing unit stm8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2.1 advanced stm8 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2.2 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3.1 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3.2 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5 low power real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.6 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.7 dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.8 analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.9 system configuration controller and routi ng interface . . . . . . . . . . . . . . . 17 3.10 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.10.1 16-bit general purpose timers (tim2, tim3) . . . . . . . . . . . . . . . . . . . . . 17 3.10.2 8-bit basic timer (tim4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.11 watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.11.1 window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.11.2 independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.12 beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.13 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.13.1 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.13.2 i 2 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.13.3 usart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.14 infrared (ir) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
stm8l051f3 contents doc id 022985 rev 1 3/46 3.15 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1 system configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5 memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.1 ecopack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.2 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.2.1 20-lead thin shrink small package (tssop20) . . . . . . . . . . . . . . . . . . . 41 7.2.2 32-pin low profile quad flat package (lqfp32) . . . . . . . . . . . . . . . . . . 42 8 device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
list of tables stm8l051f3 4/46 doc id 022985 rev 1 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. low density value line stm8l05xxx low power device features and peripheral counts. . . . 8 table 3. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4. low density value line stm8l05xxx pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 5. flash and ram boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 6. i/o port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 7. general hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 8. cpu/swim/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 9. interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 10. tssop20 20-lead thin shrink small package, mechanical data . . . . . . . . . . . . . . . . . . . . . 41 table 11. lqfp32 32-pin low profile quad flat package, mechanical data. . . . . . . . . . . . . . . . . . . . . 42 table 12. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
stm8l051f3 list of figures doc id 022985 rev 1 5/46 list of figures figure 1. low density value line stm8l05xxx device block diagram . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 2. low density value line stm8l05xxx clock tree diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 3. stm8l051fx 20-pin tssop20 package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 4. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 5. tssop20 20-lead thin shrink small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 6. tssop20 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 7. lqfp32 32-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 8. lqfp32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 figure 9. low density value line stm8l05xxx ordering information scheme . . . . . . . . . . . . . . . . . . 44
introduction stm8l051f3 6/46 doc id 022985 rev 1 1 introduction this document describes the features, pinout, mechanical data and ordering information for the low density value line stm8l151f3 microcontroller with 8-kbyte flash memory density. for more details on the whole stmicroelectronics ultra low power family please refer to section 2.2: ultra low power continuum . for detailed information on device operation and registers, refer to the reference manual (rm0031). for information on to the flash program memory and data eeprom, refer to the programming manual (pm0054). for information on the debug module and swim (single wire interface module), refer to the stm8 swim communication protocol and debug module user manual (um0470). for information on the stm8 core, refer to the stm8 cpu programming manual (pm0044). low density value line devices provide the following benefits: integrated system ? 8 kbytes of low-density embedded flash program memory ? 256 bytes of data eeprom ? 1 kbyte of ram ? internal high-speed and low-power low speed rc ? embedded reset ultra low power consumption ? 1 a in active-halt mode ? clock gated system and optimized power management ? capability to execute from ram for lo w power wait mode and low power run mode advanced features ? up to 16 mips at 16 mhz cpu clock frequency ? direct memory access (dma) for memory-to-memory or peripheral-to-memory access short development cycles ? application scalability acro ss a common family prod uct architecture with compatible pinout, memory map and modular peripherals ? wide choice of development tools these features make the value line stm8l05xxx ultra low power microcontroller family suitable for a wide range of consumer and mass market applications. refer to table 2: low density value line stm8l05xxx low power device features and peripheral counts and section 3: functional overview for an overview of the complete range of peripherals proposed in this family. figure 1 shows the block diagram of the low density value line stm8l05xxx family.
stm8l051f3 description doc id 022985 rev 1 7/46 2 description the low density value line stm8l05xxx devices are members of the stm8l ultra low power 8-bit family. the stm8l ultra low power family features an enhanced stm8 cpu core providing increased processing power (up to 16 mips at 16 mhz) while maintaining the advantages of a cisc architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low power operations. the family includes an integrated debug module with a hardware interface (swim) which allows non-intrusive in-application debugging and ultra-fast flash programming. low density value line stm8l05 xxx microcontrollers featur e embedded data eeprom and low power , low-voltage, single-supply program flash memory. the devices incorporate an extensive range of enhanced i/os and peripherals, a 12-bit adc, a real-time clock, two 16-bit timers, one 8-bit timer, as well as standard communication interfaces such as an spi, an i 2 c interface, and one usart. the modular design of the peripheral set allows the same peripherals to be found in different st microcontroller families includ ing 32-bit families. this make s any transition to a different family very easy, and simplified even more by the use of a common set of development tools. all stm8l ultra low power products are based on the same architecture with the same memory mapping and a coherent pinout.
description stm8l051f3 8/46 doc id 022985 rev 1 2.1 device overview table 2. low density value line stm8l05xxx low power device features and peripheral counts features stm8l051f3 flash (kbytes) 8 data eeprom (bytes) 256 ram (kbytes) 1 timers basic 1 (8-bit) general purpose 2 (16-bit) communicati on interfaces spi 1 i2c 1 usart 1 gpios 18 (1) 1. the number of gpios given in this table includes the nrst/pa1 pin but the application can use the nrst/pa1 pin as general purpose output only (pa1). 12-bit synchronized adc (number of channels) 1 (10) others rtc, window watchdog, independent watchdog, 16-mhz and 32-khz internal rc, 1- to 16-mhz and 32-khz external oscillator cpu frequency 16 mhz operating voltage 1.8 to 3.6 v operating temperature ?? 40 to +85 c package tssop20
stm8l051f3 description doc id 022985 rev 1 9/46 2.2 ultra low power continuum the ultra low power value line stm8l05xxx are fully pin-to-pin, software and feature compatible. besides the full compatibility wit hin the family, the devices are part of stmicroelectronics microcontrollers ultra low power strategy which also includes stm8l101xx and stm32 l15xxx. the stm8l and stm32l families allow a continuum of performance, peripherals, system architecture, and features. they are all based on stmicroelectronics 0.13 m ultralow leakage process. note: the stm8l051xx are pin-to-pin compatible with stm8l101xx devices. performance all families incorporate highly energy-efficien t cores with both harvar d architecture and pipelined execution: advanced stm8 core fo r stm8l families and arm cortex?-m3 core for stm32l family. in addition specific care for the design architecture has been taken to optimize the ma/dmips and ma/mhz ratios. this allows the ultra low power performance to range from 5 up to 33.3 dmips. shared peripherals stm8l051xx and stm32l15xx share identical peripherals which ensure a very easy migration from one family to another: analog peripheral: adc1 digital peripherals: rtc and some communication interfaces common system strategy to offer flexibility and opti mize performance, the stm8 l051xx and stm32l15xx devices use a common architecture: same power supply range from 1.65 to 3.6 v architecture optimized to reach ultra low consumption both in low power modes and run mode fast startup strategy from low power modes flexible system clock ultra-safe reset: same reset strategy for both stm8l051xx and stm32l15xx including power-on reset, power-down reset, brownout reset and programmable voltage detector. features st ultra low power continuum also lies in feature compatibility: more than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm memory density ranging from 4 to 128 kbytes
functional overview stm8l051f3 10/46 doc id 022985 rev 1 3 functional overview figure 1. low density value line stm8l05xxx device block diagram 1. legend : adc: analog-to-digital converter bor: brownout reset dma: direct memory access i2c: inter-integrated circuit multimaster interface iwdg: independent watchdog por/pdr: power-on reset / power-down reset rtc: real-time clock spi: serial peripheral interface swim: single wire interface module usart: universal synchronous as ynchronous receiver transmitter wwdg: window watchdog -36 #lock controller and#33 #locks ! d d ress co n t rol an d d at ab u ses +byte +byte2!- tocoreand peripherals )7$' k(zclock 0ort! 0ort" 0ort# 0ower 6/,42%' 77$' byte 0ort$ "eeper 24# memory 0rogram $ata%%02/- 6 $$ 6 $$ 6 $$ 6 6 33 37)- 3#,3$! 30)?-/3)30)?-)3/ 30)?3#+30)?.33 53!24?2853!24?48 53!24?#+ !$#?).x 6 $$! 6 33! 3-" 6 $$! 6 33! bit!$# 6 $$2%& 6 .234 0!;= 0";= 0#;= 0$;= "%%0 !,!2-#!,)" 4!-0 0/20$2 /3#?). /3#?/54 /3#?). /3#?/54 to "/2 06$ 06$?). 2%3%4 $-!channels channels channels )nternalreference voltage 62%&).4out )2?4)- -(zoscillator -(zinternal2# k(zoscillator 34-#ore bit4imer k(zinternal2# )nterruptcontroller bit4imer $ebugmodule 37)- bit4imer )nfraredinterface 30) )# 53!24 6 332%&
stm8l051f3 functional overview doc id 022985 rev 1 11/46 3.1 low power modes the low density value line stm8l05xxx devices support five low power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: wait mode : the cpu clock is stopped, but selected peripherals keep running. an internal or external interrupt or a reset can be used to exit the microcontroller from wait mode (wfe or wfi mode). low power run mode : the cpu and the selected peripherals are running. execution is done from ram with a low speed oscilla tor (lsi or lse). fl ash memory and data eeprom are stopped and the vo ltage regulator is configur ed in ultra low power mode. the microcontroller enters low power run mode by software and can exit from this mode by software or by a reset. all interrupts must be masked. they cannot be used to exit the microcontroller from this mode. low power wait mode: this mode is entered when executing a wait for event in low power run mode. it is similar to low power run mode except that the cpu clock is stopped. the wakeup from this mode is triggered by a reset or by an internal or external event (peripheral event generated by the timers, serial interfaces, dma controller (dma1) and i/o ports). when the wakeup is triggered by an event, the system goes back to low power run mode. all interrupts must be masked. they cannot be used to exit the microcontroller from this mode. active-halt mode : cpu and peripheral clocks are stopped, except rtc. the wakeup can be triggered by rtc interrupts, external interrupts or reset. halt mode : cpu and peripheral clocks are stopped, the device remains powered on. the ram content is preserved. the wakeup is triggered by an external interrupt or reset. a few peripherals have also a wake up from halt capability. switching off the internal reference voltage reduces power consumption. through software configuration it is also possible to wake up the device without waiting for the internal reference voltage wakeup time to have a fast wakeup time of 5 s.
functional overview stm8l051f3 12/46 doc id 022985 rev 1 3.2 central processing unit stm8 3.2.1 advanced stm8 core the 8-bit stm8 core is designed for code efficiency and performance with an harvard architecture and a 3-stage pipeline. it contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing, and 80 instructions. architecture and registers harvard architecture 3-stage pipeline 32-bit wide program memory bus - si ngle cycle fetching most instructions x and y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations 8-bit accumulator 24-bit program counter - 16-mbyte linear memory space 16-bit stack pointer - access to a 64-kbyte level stack 8-bit condition code register - 7 condition flags for the result of the last instruction addressing 20 addressing modes indexed indirect addressing mode for lookup tables located anywhere in the address space stack pointer relative addressing mode for local variables and parameter passing instruction set 80 instructions with 2-byte average instruction size standard data movement and logic/arithmetic functions 8-bit by 8-bit multiplication 16-bit by 8-bit and 16-bit by 16-bit division bit manipulation data transfer between stack and accumulator (push/pop) with direct stack access data transfer using the x and y registers or direct memory-to-memory transfers 3.2.2 interrupt controller the low density value line stm8l05xxx features a nested vectored interrupt controller: nested interrupts with 3 software priority levels 32 interrupt vectors with hardware priority up to 17 external interrupt sources on 11 vectors trap and reset interrupts
stm8l051f3 functional overview doc id 022985 rev 1 13/46 3.3 reset and supply management 3.3.1 power supply scheme the device requires a 1.8 v to 3.6 v operating supply voltage (v dd ). the external power supply pins must be connected as follows: v ss1 ; v dd1 = 1.8 to 3.6 v: external power supply for i/os and for the internal regulator. provided externally through v dd1 pins, the corresponding ground pin is v ss1 . v ssa ; v dda = 1.8 to 3.6 v: external power supplies for analog peripherals. v dda and v ssa must be connected to v dd1 and v ss1 , respectively. v ss2 ; v dd2 = 1.8 to 3.6 v: external power supplies for i/os. v dd2 and v ss2 must be connected to v dd1 and v ss1 , respectively. v ref+ , v ref- (for adc1): external reference voltage for adc1. must be provided externally through v ref+ and v ref- pin. 3.3.2 power supply supervisor the device has an integrated zeropower power-on reset (por)/power-down reset (pdr), coupled with a brownout reset (bor) circuitry. when the microcontroller operates between 1.8 and 3.6 v, bor is always active and ensures proper operation starting from 1.8 v. after the 1.8 v bor threshold is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable bor permanently. five bor thresholds are available through option bytes, starting from 1.8 v to 3 v. to reduce the power consumption in halt mode, it is possible to automatically switch off the internal reference voltage (and consequently the bor) in halt mode. the device remains in reset state when v dd is below a specified threshold, v por/pdr or v bor , without the need for any external reset circuit. the device features an embedded programmable voltage detector (pvd) that monitors the v dd /v dda power supply and compares it to the v pvd threshold. this pvd offers 7 different levels between 1.85 v and 3.05 v, chosen by software, with a step around 200 mv. an interrupt can be generated when v dd /v dda drops below the v pvd threshold and/or when v dd /v dda is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. 3.3.3 voltage regulator the low density value line stm8l05xxx embeds an internal voltage regulator for generating the 1.8 v power supply for the core and peripherals. this regulator has two different modes: main voltage regulator mode (mv r) for run, wait for interrupt (wfi) and wait for event (wfe) modes. low power voltage regulator mode (lpvr) for halt, active-halt, low power run and low power wait modes. when entering halt or active-halt modes, the system automatically switches from the mvr to the lpvr in order to reduce current consumption.
functional overview stm8l051f3 14/46 doc id 022985 rev 1 3.4 clock management the clock controller distributes the system clock (sysclk) coming from different oscillators to the core and the peripherals. it also manages clock gating for low power modes and ensures clock robustness. features clock prescaler: to get the best compromise between speed and current consumption the clock frequency to the cpu and peripherals can be adjusted by a programmable prescaler. safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. system clock sources: four different clock sources can be used to drive the system clock: ? 1-16 mhz high speed external crystal (hse) ? 16 mhz high speed internal rc oscillator (hsi) ? 32.768 low speed external crystal (lse) ? 38 khz low speed internal rc (lsi) rtc clock sources: the above four sources can be chosen to clock the rtc whatever the system clock. startup clock: after reset, the microcontroller restarts by default with an internal 2 mhz clock (hsi/8). the prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. clock security system (css): this feature can be enabled by software. if a hse clock failure occurs, it is auto matically switched to hsi. configurable main clock output (cco): this outputs an external clock for use by the application.
stm8l051f3 functional overview doc id 022985 rev 1 15/46 figure 2. low density value line stm8l05xxx clock tree diagram 1. the hse clock source can be either an external crystal/ceramic res onator or an external source (hse bypass). refer to section hse clock in the st m8l15x and stm8l16x reference manual (rm0031). 2. the lse clock source can be either an external crystal/ceramic resonat or or a external source (lse bypass). refer to section lse clock in the stm8l15x and stm8l16x reference manual (rm0031). /3#?/54 /3#?). (3% (3) ,3) ,3% ,3% ,3) (3%/3# -(z (3)2# -(z ,3)2# k(z ,3%/3# k(z /3#?/54 /3#?). ##/ #onfigurable clockoutput prescaler ##/ (3% (3) ,3) ,3% prescaler 393#,+ 393#,+tocoreand memory 0#,+to peripherals 0eripheral #lock #,+"%%03%,;= )7$'#,+ "%%0#,+ 24##,+ enablebits 24#3%,;= 24# prescaler to "%%0 to )7$' to 24# -36 37)-;= ##/3%,;=
functional overview stm8l051f3 16/46 doc id 022985 rev 1 3.5 low power real-time clock the real-time clock (rtc) is an independent binary coded decimal (bcd) timer/counter. six byte locations contain the second, minute, hour (12/24 hour), week day, date, month, year, in bcd (binary coded decimal) format. correction for 28, 29 (leap year), 30, and 31 day months are made automatically. it provides a programmable alarm and programmable periodic interrupts with wakeup from halt capability. periodic wakeup time using the 32.768 khz lse with the lowest resolution (of 61 s) is from min. 122 s to max. 3.9 s. with a different resolution, the wakeup time can reach 36 hours periodic alarms based on the calendar can also be generated from every second to every year 3.6 memories the low density value line st m8l05xxx devices have the following main features: up to 1 kbyte of ram the non-volatile memory is divided into three arrays: ? 8 kbytes of low-density embedded flash program memory ? 256 bytes of data eeprom ?option bytes the eeprom embeds the error corr ection code (ecc) feature. the option byte protects part of the flash program memory from write and readout piracy. 3.7 dma a 4-channel direct memory access controlle r (dma1) offers a memory-to-memory and peripherals-from/to-memory tr ansfer capability. the 4 chann els are shared between the following ips with dma capability: adc1, i2c1 , spi1, usart1, and the three timers. 3.8 analog-to-digital converter 12-bit analog-to-digital converter (adc1) with 10 channels (including 1 fast channel) and internal reference voltage conversion time down to 1 s with f sysclk = 16 mhz programmable resolution programmable sampling time single and continuous mode of conversion scan capability: automatic conversion perfor med on a selected gr oup of anal og inputs analog watchdog triggered by timer note: adc1 can be served by dma1.
stm8l051f3 functional overview doc id 022985 rev 1 17/46 3.9 system configuration cont roller and routing interface the system configuration controller provides the capability to remap some alternate functions on different i/o ports. tim4 and adc1 dma channels can also be remapped. the highly flexible routing interface controls the routing of internal analog signals to adc1 and the internal reference voltage v refint . 3.10 timers low density value line stm8l05xxx devices contain two 16-bit general purpose timers (tim2 and tim3) and one 8-bit basic timer (tim4). all the timers can be served by dma1. ta bl e 3 compares the features of the advanced control, general-purpose and basic timers. 3.10.1 16-bit general purpos e timers (tim2, tim3) 16-bit autoreload (ar) up/down-counter 7-bit prescaler adjustable to fixed power of 2 ratios (1?128) 2 individually configurable capture/compare channels pwm mode interrupt capability on various events (cap ture, compare, overflow, break, trigger) synchronization with other timers or external signals (external clock, reset, trigger and enable) 3.10.2 8-bit basi c timer (tim4) the 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable prescaler. it can be used for timebase generation with interrupt generation on timer overflow. 3.11 watchdog timers the watchdog system is based on two independent timers providing maximum security to the applications. table 3. timer feature comparison timer counter resolution counter type prescaler factor dma1 request generation capture/compare channels complementary outputs tim2 16-bit up/down any power of 2 from 1 to 128 ye s 2 none tim3 tim4 8-bit up any power of 2 from 1 to 32768 0
functional overview stm8l051f3 18/46 doc id 022985 rev 1 3.11.1 window watchdog timer the window watchdog (wwdg) is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. 3.11.2 independent watchdog timer the independent watchdog peripheral (iwdg) can be used to resolve processor malfunctions due to hardware or software failures. it is clocked by the internal lsi rc clock source, and thus stays active even in case of a cpu clock failure. 3.12 beeper the beeper functi on outputs a signal on the beep pin for sound gener ation. the signal is in the range of 1, 2 or 4 khz. 3.13 communication interfaces 3.13.1 spi the serial peripheral interfaces (spi1) provide half/ full duplex synchronous serial communication with external devices. maximum speed: 8 mbit/s (f sysclk /2) both for master and slave full duplex synchronous transfers simplex synchronous transfers on 2 lines with a possible bidirectional data line master or slave operation - selectable by hardware or software hardware crc calculation slave/master selection input pin note: spi1 can be served by the dma1 controller. 3.13.2 i 2 c the i 2 c bus interface (i2c1) provi des multi-master capability, and controls all i2c bus- specific sequencing, protocol, arbitration and timing. master, slave and multi-master capability standard mode up to 100 khz and fast speed modes up to 400 khz 7-bit and 10-bit addressing modes smbus 2.0 and pmbus support hardware crc calculation note: i 2 c1 can be served by the dma1 controller.
stm8l051f3 functional overview doc id 022985 rev 1 19/46 3.13.3 usart the usart interface (usart1) allows full duplex, asynchronous communications with external devices requiring an industry standard nrz asynchronous serial data format. it offers a very wide range of baud rates. 1 mbit/s full duplex sci spi1 emulation high precision baud rate generator smartcard emulation irda sir encoder decoder single wire half duplex mode note: usart1 can be served by the dma1 controller. 3.14 infrared (ir) interface the low density stm8l05xxx devices contain an infrared interface which can be used with an ir led for remote control functions. two timer output compare channels are used to generate the infrared remote control signals. 3.15 development support development tools development tools for the stm8 microcontrollers include: the stice emulation system offe ring tracing and code profiling the stvd high-level language debugger including c compiler, assembler and integrated development environment the stvp flash programming software the stm8 also comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools. single wire data interface (swim) and debug module the debug module with its single wire data interface (swim) permits non-intrusive real-time in-circuit debugging and fast memory programming. the single wire interface is used for direct access to the debugging module and memory programming. the interface can be activated in all device operation modes. the non-intrusive debugging module features a performance close to a full-featured emulator. beside memory and peripherals, cpu operation can also be monitored in real- time by means of shadow registers.
functional overview stm8l051f3 20/46 doc id 022985 rev 1 bootloader the low density value line stm8l05xxx ultra low power devices feature a built-in bootloader (see um0560: stm8 bootloader user manual ). the bootloader is used to download application software into the device memories, including ram, program and data memory, using standard serial interfaces. it is a complementary solution to programming via the swim debugging interface.
stm8l051f3 pin description doc id 022985 rev 1 21/46 4 pin description figure 3. stm8l051fx 20-pin tssop20 package pinout 0! 0! 6 33 6 33! 6 2%& .2340! 0# 0# 0" 0" 0" 0" 0" 0" 0" 6 $$ 6 $$! 6 2%& 0# -36 0" 0$ 0! 0# 0# table 4. low density value line stm8l05xxx pin description pin n pin name type input output main function (after reset) default alternate function tssop20 floating wpu ext. interrupt high sink/source od pp 4 nrst/pa1 (1) i/o x hs x reset pa 1 5 pa 2 / o s c _ i n / [usart_tx] (2) / [spi_miso] (2) i/o x xxhsxx port a2 hse oscillator input / [usart transmit] / [spi master in- slave out] 6 pa 3 / o s c _ o u t / [usart_rx] (2) /[ spi_mosi] (2) i/o x xxhsxx port a3 hse oscillator output / [usart receive]/ [spi master out/slave in] / 10 pb0 (3) /tim2_ch1/adc1_in18 i/o x xxhsxx port b0 timer 2 - channel 1 / adc1_in18 11 pb1/tim3_ch1/adc1_in17 i/o x xxhsxx port b1 timer 3 - channel 1 / adc1_in17 12 pb2/ tim2_ch2/ adc1_in16 i/o x xxhsxx port b2 timer 2 - channel 2 adc1_in16 13 pb3/tim2_etr/ adc1_in15/rtc_alarm i/o x xxhsxx port b3 timer 2 - external trigger / adc1_in15 / rtc_alarm 14 pb4 (3) /spi1_nss/adc1_in14 i/o x xxhsxx port b4 spi master/slave select / adc1_in14 15 pb5/spi_sck/ /adc1_in13 i/o x xxhsxx port b5 [spi clock] / adc1_in13 16 pb6/spi1_mosi/ adc1_in12 i/o x xxhsxx port b6 spi master out/ slave in / adc1_in12
pin description stm8l051f3 22/46 doc id 022985 rev 1 note: the slope control of all gpio pins, except true open drain pins, can be programmed. by default, the slope control is limited to 2 mhz. 17 pb7/spi1_miso/adc1_in11 i/o x xxhsxx port b7 spi1 master in- slave out/ adc1_in11 18 pc0/i2c_sda i/o x xt (4) port c0 i2c data 19 pc1/i2c_scl i/o x xt (3) port c1 i2c clock 20 pc4/usart_ck]/ i2c_smb/cco/adc1_in4 i/o x xxhsxx port c4 usart synchronous clock / i2c1_smb / configurable clock output / adc1_in4 1 pc5/osc32_in / [spi1_nss] (2) / [usart_tx] (2) /tim2_ch1 i/o x xxhsxx port c5 lse oscillator input / [spi master/slave select] / [usart transmit]/timer 2 -channel 1 2 pc6/osc32_out/ [spi_sck] (2) /[ usart_rx] (2) /tim2_ch2 i/o x xxhsxx port c6 lse oscillator output / [spi clock] / [usart receive]/ timer 2 -channel 2 9 pd0/tim3_ch2/ [adc1_trig] (2) / adc1_in22 i/o x xxhsxx port d0 timer 3 - channel 2 / [adc1_trigger] / adc1_in22 8v dd / v dda / v ref+ s digital supply voltage / adc1 positive voltage reference 7v ss / v ref- / v ssa ground voltage / adc1 negative voltage reference / analog ground voltage 3 pa 0 (5) / [usart_ck] (2) / swim/beep/ir_tim (6) i/o x x x hs (6) xx port a0 [usart1 synchronous clock] (2) / swim input and output / beep output / infrared timer output 1. at power-up, the pa1/nrst pin is a reset input pin with pull-up. to be used as a general purpose pin (pa1), it can be configured only as output open-drai n or push-pull, not as a general purpose input. refer to section configuring nrst/pa1 pin as general purpose output in the stm8l15xxx and stm8l16x xx reference manual (rm0031). 2. [ ] alternate function remapping option (if the same alternate function is shown twice, it i ndicates an exclusive choice not a duplication of the function). 3. a pull-up is applied to pb0 and pb4 during the reset phase . these two pins are input floating after reset release. 4. in the open-drain output column, ?t? defines a true open-drain i/o (p-buffer and protection diode to v dd are not implemented). 5. the pa0 pin is in input pull-up during the reset phase and after reset release. 6. high sink led driver capability available on pa0. table 4. low density value line stm8l05xxx pin description (continued) pin n pin name type input output main function (after reset) default alternate function tssop20 floating wpu ext. interrupt high sink/source od pp
stm8l051f3 pin description doc id 022985 rev 1 23/46 4.1 system configuration options as shown in table 4: low density value line stm8l05xxx pin description , some alternate functions can be remapped on different i/o ports by programming one of the two remapping registers described in the ? routing interface (ri) and system configuration controller? section in the stm8l15xx and stm8l16xx reference manual (rm0031).
memory and register map stm8l051f3 24/46 doc id 022985 rev 1 5 memory and register map 5.1 memory mapping the memory map is shown in figure 4 . figure 4. memory map 1. table 5 lists the boundary addresses for each memory si ze. the top of the stack is at the ram end address. 2. refer to table 7 for an overview of hardware register mapping, to table 6 for details on i/o port hardware registers, and to table 8 for information on cpu/swim/debug module controller registers. '0)/andperipheralregisters x ,owdensity +bytes 2esetandinterruptvectors x&& 2!- x && +byte bytes x $a ta %%0 2/ - x x & x x &&& x x &&& x x && x%&& x x&& x& 2eserved in cl ud in g 3ta ck "ytes /ptionbytes x &&& x x x 2e ser ved x &&& "oo t2/- x x && +bytes x 2e ser ved #0537)-$ebug)4# 2egisters &lashprogrammemory 2e ser ved -36 6qup 2eserved x x &&& 2) 2eserved x x% x x x x$ x! x! x!! x! x" x" x" x# x$ x$ x$ x% x% x& x& x x x x x x& x x" x x x x x% x%! x&& x x x# x x x x 2eserved '0)/ports &lash 2eserved $-! 393#&' )4# %84 7&% 234 072 #,+ 77$' )4# %84 2eserved 2eserved 2eserved 2eserved 2eserved 2eserved 2eserved 2eserved 2eserved 2eserved 2eserved 2eserved )7$' "%%0 24# 30) )# 53!24 4)- 4)- 2eserved 2eserved 2eserved 4)- )24)- !$# 2)
stm8l051f3 memory and register map doc id 022985 rev 1 25/46 5.2 register map table 5. flash and ram boundary addresses memory area size start address end address ram 1 kbyte 0x00 0000 0x00 03ff flash program memory 8 kbytes 0x00 8000 0x00 9fff table 6. i/o port hardware register map address block register label register name reset status 0x00 5000 port a pa_odr port a data output latch register 0x00 0x00 5001 pa_idr port a input pin value register 0xxx 0x00 5002 pa_ddr port a data direction register 0x00 0x00 5003 pa_cr1 port a control register 1 0x01 0x00 5004 pa_cr2 port a control register 2 0x00 0x00 5005 port b pb_odr port b data output latch register 0x00 0x00 5006 pb_idr port b input pin value register 0xxx 0x00 5007 pb_ddr port b data direction register 0x00 0x00 5008 pb_cr1 port b control register 1 0x00 0x00 5009 pb_cr2 port b control register 2 0x00 0x00 500a port c pc_odr port c data output latch register 0x00 0x00 500b pb_idr port c input pin value register 0xxx 0x00 500c pc_ddr port c data direction register 0x00 0x00 500d pc_cr1 port c control register 1 0x00 0x00 500e pc_cr2 port c control register 2 0x00 0x00 500f port d pd_odr port d data output latch register 0x00 0x00 5010 pd_idr port d input pin value register 0xxx 0x00 5011 pd_ddr port d data direction register 0x00 0x00 5012 pd_cr1 port d control register 1 0x00 0x00 5013 pd_cr2 port d control register 2 0x00 0x00 5014 to 0x00 501d reserved area (0 bytes)
memory and register map stm8l051f3 26/46 doc id 022985 rev 1 table 7. general hardware register map address block register label register name reset status 0x00 502e to 0x00 5049 reserved area (44 bytes) 0x00 5050 flash flash_cr1 flash control register 1 0x00 0x00 5051 flash_cr2 flash control register 2 0x00 0x00 5052 flash _pukr flash program memory unprotection key register 0x00 0x00 5053 flash _dukr data eeprom unprotection key register 0x00 0x00 5054 flash _iapsr flash in-application programming status register 0x00 0x00 5055 to 0x00 506f reserved area (27 bytes) 0x00 5070 dma1 dma1_gcsr dma1 global configuration & status register 0xfc 0x00 5071 dma1_gir1 dma1 global interrupt register 1 0x00 0x00 5072 to 0x00 5074 reserved area (3 bytes) 0x00 5075 dma1_c0cr dma1 channel 0 configuration register 0x00 0x00 5076 dma1_c0spr dma1 channel 0 status & priority register 0x00 0x00 5077 dma1_c0ndtr dma1 number of data to transfer register (channel 0) 0x00 0x00 5078 dma1_c0parh dma1 peripheral address high register (channel 0) 0x52 0x00 5079 dma1_c0parl dma1 peripheral address low register (channel 0) 0x00 0x00 507a reserved area (1 byte) 0x00 507b dma1_c0m0arh dma1 memory 0 address high register (channel 0) 0x00 0x00 507c dma1_c0m0arl dma1 memory 0 address low register (channel 0) 0x00
stm8l051f3 memory and register map doc id 022985 rev 1 27/46 0x00 507d to 0x00 507e dma1 reserved area (2 bytes) 0x00 507f dma1_c1cr dma1 channel 1 configuration register 0x00 0x00 5080 dma1_c1spr dma1 channel 1 status & priority register 0x00 0x00 5081 dma1_c1ndtr dma1 number of data to transfer register (channel 1) 0x00 0x00 5082 dma1_c1parh dma1 peripheral address high register (channel 1) 0x52 0x00 5083 dma1_c1parl dma1 peripheral address low register (channel 1) 0x00 0x00 5084 reserved area (1 byte) 0x00 5085 dma1_c1m0arh dma1 memory 0 address high register (channel 1) 0x00 0x00 5086 dma1_c1m0arl dma1 memory 0 address low register (channel 1) 0x00 0x00 5087 0x00 5088 reserved area (2 bytes) 0x00 5089 dma1_c2cr dma1 channel 2 configuration register 0x00 0x00 508a dma1_c2spr dma1 channel 2 status & priority register 0x00 0x00 508b dma1_c2ndtr dma1 number of data to transfer register (channel 2) 0x00 0x00 508c dma1_c2parh dma1 peripheral address high register (channel 2) 0x52 0x00 508d dma1_c2parl dma1 peripheral address low register (channel 2) 0x00 0x00 508e reserved area (1 byte) 0x00 508f dma1_c2m0arh dma1 memory 0 address high register (channel 2) 0x00 0x00 5090 dma1_c2m0arl dma1 memory 0 address low register (channel 2) 0x00 0x00 5091 0x00 5092 reserved area (2 bytes) 0x00 5093 dma1_c3cr dma1 channel 3 configuration register 0x00 0x00 5094 dma1_c3spr dma1 channel 3 status & priority register 0x00 0x00 5095 dma1_c3ndtr dma1 number of data to transfer register (channel 3) 0x00 0x00 5096 dma1_c3parh_ c3m1arh dma1 peripheral address high register (channel 3) 0x40 0x00 5097 dma1_c3parl_ c3m1arl dma1 peripheral address low register (channel 3) 0x00 table 7. general hardware register map (continued) address block register label register name reset status
memory and register map stm8l051f3 28/46 doc id 022985 rev 1 0x00 5098 dma1 dma_c3m0ear dma channel 3 memory 0 extended address register 0x00 0x00 5099 dma1_c3m0arh dma1 memory 0 address high register (channel 3) 0x00 0x00 509a dma1_c3m0arl dma1 memory 0 address low register (channel 3) 0x00 0x00 509b to 0x00 509c reserved area (3 bytes) 0x00 509d syscfg syscfg_rmpcr3 remapping register 3 0x00 0x00 509e syscfg_rmpcr1 remapping register 1 0x00 0x00 509f syscfg_rmpcr2 remapping register 2 0x00 0x00 50a0 itc - exti exti_cr1 external interrup t control register 1 0x00 0x00 50a1 exti_cr2 external interrupt control register 2 0x00 0x00 50a2 exti_cr3 external interrupt control register 3 0x00 0x00 50a3 exti_sr1 external interrupt status register 1 0x00 0x00 50a4 exti_sr2 external interrupt status register 2 0x00 0x00 50a5 exti_conf1 external interrupt port select register 1 0x00 0x00 50a6 wfe wfe_cr1 wfe control register 1 0x00 0x00 50a7 wfe_cr2 wfe control register 2 0x00 0x00 50a8 wfe_cr3 wfe control register 3 0x00 0x00 50a9 wfe_cr4 wfe control register 4 0x00 0x00 50aa itc - exti exti_cr4 external interrup t control register 4 0x00 0x00 50ab exti_conf2 external interrupt port select register 2 0x00 0x00 50a9 to 0x00 50af reserved area (7 bytes) 0x00 50b0 rst rst_cr reset control register 0x00 0x00 50b1 rst_sr reset status register 0x01 0x00 50b2 pwr pwr_csr1 power control and status register 1 0x00 0x00 50b3 pwr_csr2 power control and status register 2 0x00 0x00 50b4 to 0x00 50bf reserved area (12 bytes) 0x00 50c0 clk clk_ckdivr clk clock master divider register 0x03 0x00 50c1 clk_crtcr clk clock rtc register 0x00 (1) 0x00 50c2 clk_ickcr clk internal clock control register 0x11 0x00 50c3 clk_pckenr1 clk peripheral clock gating register 1 0x00 table 7. general hardware register map (continued) address block register label register name reset status
stm8l051f3 memory and register map doc id 022985 rev 1 29/46 0x00 50c4 clk clk_pckenr2 clk peripheral clock gating register 2 0x00 0x00 50c5 clk_ccor clk configurable clock control register 0x00 0x00 50c6 clk_eckcr clk external clock control register 0x00 0x00 50c7 clk_scsr clk system clock status register 0x01 0x00 50c8 clk_swr clk system clock switch register 0x01 0x00 50c9 clk_swcr clk clock switch control register 0xx0 0x00 50ca clk_cssr clk clock se curity system register 0x00 0x00 50cb clk_cbeepr clk clock beep register 0x00 0x00 50cc clk_hsicalr clk hsi calibration register 0xxx 0x00 50cd clk_hsitrimr clk hsi clock calibration trimming register 0x00 0x00 50ce clk_hsiunlckr clk hsi unlock register 0x00 0x00 50cf clk_regcsr clk main regulator control status register 0bxx11 1 00x 0x00 50d0 clk_pckenr3 clk peripheral clock gating register 3 0x00 0x00 50d1 to 0x00 50d2 reserved area (2 bytes) 0x00 50d3 wwdg wwdg_cr wwdg control register 0x7f 0x00 50d4 wwdg_wr wwdr window register 0x7f 0x00 50d5 to 00 50df reserved area (11 bytes) 0x00 50e0 iwdg iwdg_kr iwdg key register 0x01 0x00 50e1 iwdg_pr iwdg prescaler register 0x00 0x00 50e2 iwdg_rlr iwdg reload register 0xff 0x00 50e3 to 0x00 50ef reserved area (13 bytes) 0x00 50f0 beep beep_csr1 beep control/status register 1 0x00 0x00 50f1 0x00 50f2 reserved area (2 bytes) 0x00 50f3 beep_csr2 beep control/status register 2 0x1f 0x00 50f4 to0x00 513f reserved area (76 bytes) 0x00 5140 rtc rtc_tr1 rtc time register 1 0x00 0x00 5141 rtc_tr2 rtc time register 2 0x00 0x00 5142 rtc_tr3 rtc time register 3 0x00 table 7. general hardware register map (continued) address block register label register name reset status
memory and register map stm8l051f3 30/46 doc id 022985 rev 1 0x00 5143 rtc reserved area (1 byte) 0x00 5144 rtc_dr1 rtc date register 1 0x01 0x00 5145 rtc_dr2 rtc date register 2 0x21 0x00 5146 rtc_dr3 rtc date register 3 0x00 0x00 5147 reserved area (1 byte) 0x00 5148 rtc_cr1 rtc control register 1 0x00 (1) 0x00 5149 rtc_cr2 rtc control register 2 0x00 (1) 0x00 514a rtc_cr3 rtc control register 3 0x00 (1) 0x00 514b reserved area (1 byte) 0x00 514c rtc_isr1 rtc initializati on and status register 1 0x01 0x00 514d rtc_isr2 rtc initialization and status register 2 0x00 0x00 514e 0x00 514f reserved area (2 bytes) 0x00 5150 rtc_sprerh rtc synchronous prescaler register high 0x00 (1) 0x00 5151 rtc_sprerl rtc synchronous prescaler register low 0xff (1) 0x00 5152 rtc_aprer rtc asynchronous prescaler register 0x7f (1) 0x00 5153 reserved area (1 byte) 0x00 5154 rtc_wutrh rtc wakeup timer register high 0xff (1) 0x00 5155 rtc_wutrl rtc wakeup timer register low 0xff (1) 0x00 5156 reserved area (1 byte) 0x00 5157 rtc_ssrl rtc subsecond register low 0x00 0x00 5158 rtc_ssrh rtc subsecond register high 0x00 0x00 5159 rtc_wpr rtc write protection register 0x00 0x00 5158 rtc_ssrh rtc subsecond register high 0x00 0x00 5159 rtc_wpr rtc write protection register 0x00 0x00 515a rtc_shiftrh rtc shift register high 0x00 0x00 515b rtc_shiftrl rtc shift register low 0x00 0x00 515c rtc_alrmar1 rtc alarm a register 1 0x00 (1) 0x00 515d rtc_alrmar2 rtc alarm a register 2 0x00 (1) 0x00 515e rtc_alrmar3 rtc alarm a register 3 0x00 (1) 0x00 515f rtc_alrmar4 rtc alarm a register 4 0x00 (1) 0x00 5160 to 0x00 5163 reserved area (4 bytes) 0x00 5164 rtc_alrmassrh rtc alarm a subsecond register high 0x00 (1) 0x00 5165 rtc_alrmassrl rtc alarm a subsecond register low 0x00 (1) table 7. general hardware register map (continued) address block register label register name reset status
stm8l051f3 memory and register map doc id 022985 rev 1 31/46 0x00 5166 rtc rtc_alrmassmskr rtc alarm a masking register 0x00 (1) 0x00 5167 to 0x00 5169 reserved area (3 bytes) 0x00 516a rtc_calrh rtc calibration register high 0x00 (1) 0x00 516b rtc_calrl rtc calibration register low 0x00 (1) 0x00 516c rtc_tcr1 rtc tamper control register 1 0x00 (1) 0x00 516d rtc_tcr2 rtc tamper control register 2 0x00 (1) 0x00 516e to 0x00 518a reserved area (36 bytes) 0x00 5190 csslse_csr css on lse control and status register 0x00 (1) 0x00 519a to 0x00 51ff reserved area (111 bytes) 0x00 5200 spi1 spi1_cr1 spi1 control register 1 0x00 0x00 5201 spi1_cr2 spi1 control register 2 0x00 0x00 5202 spi1_icr spi1 interrupt control register 0x00 0x00 5203 spi1_sr spi1 status register 0x02 0x00 5204 spi1_dr spi1 data register 0x00 0x00 5205 spi1_crcpr spi1 crc polynomial register 0x07 0x00 5206 spi1_rxcrcr spi1 rx crc register 0x00 0x00 5207 spi1_txcrcr spi1 tx crc register 0x00 0x00 5208 to 0x00 520f reserved area (8 bytes) 0x00 5210 i2c1 i2c1_cr1 i2c1 control register 1 0x00 0x00 5211 i2c1_cr2 i2c1 control register 2 0x00 0x00 5212 i2c1_freqr i2c1 frequency register 0x00 0x00 5213 i2c1_oarl i2c1 own address register low 0x00 0x00 5214 i2c1_oarh i2c1 own address register high 0x00 0x00 5215 i2c1_oar2 i2c1 own address register for dual mode 0x00 0x00 5216 i2c1_dr i2c1 data register 0x00 0x00 5217 i2c1_sr1 i2c1 status register 1 0x00 0x00 5218 i2c1_sr2 i2c1 status register 2 0x00 0x00 5219 i2c1_sr3 i2c1 status register 3 0x0x 0x00 521a i2c1_itr i2c1 interrupt control register 0x00 0x00 521b i2c1_ccrl i2c1 clock control register low 0x00 0x00 521c i2c1_ccrh i2c1 clock control register high 0x00 table 7. general hardware register map (continued) address block register label register name reset status
memory and register map stm8l051f3 32/46 doc id 022985 rev 1 0x00 521d i2c1 i2c1_triser i2c1 trise register 0x02 0x00 521e i2c1_pecr i2c1 packet error checking register 0x00 0x00 521f to 0x00 522f reserved area (17 bytes) 0x00 5230 usart1 usart1_sr usart1 status register 0xc0 0x00 5231 usart1_dr usart1 data register 0xxx 0x00 5232 usart1_brr1 usart1 baud rate register 1 0x00 0x00 5233 usart1_brr2 usart1 baud rate register 2 0x00 0x00 5234 usart1_cr1 usart1 control register 1 0x00 0x00 5235 usart1_cr2 usart1 control register 2 0x00 0x00 5236 usart1_cr3 usart1 control register 3 0x00 0x00 5237 usart1_cr4 usart1 control register 4 0x00 0x00 5238 usart1_cr5 usart1 control register 5 0x00 0x00 5239 usart1_gtr usart1 guard time register 0x00 0x00 523a usart1_pscr usart1 prescaler register 0x00 0x00 523b to 0x00 524f reserved area (21 bytes) 0x00 5250 tim2 tim2_cr1 tim2 contro l register 1 0x00 0x00 5251 tim2_cr2 tim2 co ntrol register 2 0x00 0x00 5252 tim2_smcr tim2 slave mode control register 0x00 0x00 5253 tim2_etr tim2 external trigger register 0x00 0x00 5254 tim2_der tim2 dma1 request enable register 0x00 0x00 5255 tim2_ier tim2 interrupt enable register 0x00 0x00 5256 tim2_sr1 tim2 st atus register 1 0x00 0x00 5257 tim2_sr2 tim2 st atus register 2 0x00 0x00 5258 tim2_egr tim2 event generation register 0x00 0x00 5259 tim2_ccmr1 tim2 capture/compare mode register 1 0x00 0x00 525a tim2_ccmr2 tim2 capture/compare mode register 2 0x00 0x00 525b tim2_ccer1 tim2 capture/compare enable register 1 0x00 0x00 525c tim2_cntrh tim2 counter high 0x00 0x00 525d tim2_cntrl tim2 counter low 0x00 0x00 525e tim2_pscr tim2 prescaler register 0x00 0x00 525f tim2_arrh tim2 auto-reload register high 0xff table 7. general hardware register map (continued) address block register label register name reset status
stm8l051f3 memory and register map doc id 022985 rev 1 33/46 0x00 5260 tim2 tim2_arrl tim2 auto-reload register low 0xff 0x00 5261 tim2_ccr1h tim2 capture/ compare register 1 high 0x00 0x00 5262 tim2_ccr1l tim2 captur e/compare register 1 low 0x00 0x00 5263 tim2_ccr2h tim2 capture/ compare register 2 high 0x00 0x00 5264 tim2_ccr2l tim2 captur e/compare register 2 low 0x00 0x00 5265 tim2_bkr tim2 break register 0x00 0x00 5266 tim2_oisr tim2 output idle state register 0x00 0x00 5267 to 0x00 527f reserved area (25 bytes) 0x00 5280 tim3 tim3_cr1 tim3 contro l register 1 0x00 0x00 5281 tim3_cr2 tim3 co ntrol register 2 0x00 0x00 5282 tim3_smcr tim3 slave mode control register 0x00 0x00 5283 tim3_etr tim3 external trigger register 0x00 0x00 5284 tim3_der tim3 dma1 request enable register 0x00 0x00 5285 tim3_ier tim3 interrupt enable register 0x00 0x00 5286 tim3_sr1 tim3 st atus register 1 0x00 0x00 5287 tim3_sr2 tim3 st atus register 2 0x00 0x00 5288 tim3_egr tim3 event generation register 0x00 0x00 5289 tim3_ccmr1 tim3 capture/compare mode register 1 0x00 0x00 528a tim3_ccmr2 tim3 capture/compare mode register 2 0x00 0x00 528b tim3_ccer1 tim3 captur e/compare enable register 1 0x00 0x00 528c tim3_cntrh tim3 counter high 0x00 0x00 528d tim3_cntrl tim3 counter low 0x00 0x00 528e tim3_pscr tim3 prescaler register 0x00 0x00 528f tim3_arrh tim3 auto-reload register high 0xff 0x00 5290 tim3_arrl tim3 auto-reload register low 0xff 0x00 5291 tim3_ccr1h tim3 capture/ compare register 1 high 0x00 0x00 5292 tim3_ccr1l tim3 capture/compare register 1 low 0x00 0x00 5293 tim3_ccr2h tim3 capture/ compare register 2 high 0x00 0x00 5294 tim3_ccr2l tim3 capture/compare register 2 low 0x00 0x00 5295 tim3_bkr tim3 break register 0x00 0x00 5296 tim3_oisr tim3 output idle state register 0x00 0x00 5297 to 0x00 52df reserved area (72 bytes) table 7. general hardware register map (continued) address block register label register name reset status
memory and register map stm8l051f3 34/46 doc id 022985 rev 1 0x00 52e0 tim4 tim4_cr1 tim4 contro l register 1 0x00 0x00 52e1 tim4_cr2 tim4 control register 2 0x00 0x00 52e2 tim4_smcr tim4 slav e mode control register 0x00 0x00 52e3 tim4_der tim4 dma1 request enable register 0x00 0x00 52e4 tim4_ier tim4 interrupt enable register 0x00 0x00 52e5 tim4_sr1 tim4 status register 1 0x00 0x00 52e6 tim4_egr tim4 event generation register 0x00 0x00 52e7 tim4_cntr tim4 counter 0x00 0x00 52e8 tim4_pscr tim4 prescaler register 0x00 0x00 52e9 tim4_arr tim4 auto-reload register 0x00 0x00 52ea to 0x00 52fe reserved area (21 bytes) 0x00 52ff irtim ir_cr infrared control register 0x00 0x00 5317 to 0x00 533f reserved area (41 bytes) 0x00 5340 adc1 adc1_cr1 adc1 configuration register 1 0x00 0x00 5341 adc1_cr2 adc1 configuration register 2 0x00 0x00 5342 adc1_cr3 adc1 configuration register 3 0x1f 0x00 5343 adc1_sr adc1 status register 0x00 0x00 5344 adc1_drh adc1 data register high 0x00 0x00 5345 adc1_drl adc1 data register low 0x00 0x00 5346 adc1_htrh adc1 high threshold register high 0x0f 0x00 5347 adc1_htrl adc1 high threshold register low 0xff 0x00 5348 adc1_ltrh adc1 low threshold register high 0x00 0x00 5349 adc1_ltrl adc1 low threshold register low 0x00 0x00 534a adc1_sqr1 adc1 channel sequence 1 register 0x00 0x00 534b adc1_sqr2 adc1 channel sequence 2 register 0x00 0x00 534c adc1_sqr3 adc1 channel sequence 3 register 0x00 0x00 534d adc1_sqr4 adc1 channel sequence 4 register 0x00 0x00 534e adc1_trigr1 adc1 trigger disable 1 0x00 0x00 534f adc1_trigr2 adc1 trigger disable 2 0x00 0x00 5350 adc1_trigr3 adc1 trigger disable 3 0x00 0x00 5351 adc1_trigr4 adc1 trigger disable 4 0x00 table 7. general hardware register map (continued) address block register label register name reset status
stm8l051f3 memory and register map doc id 022985 rev 1 35/46 0x00 53c8 to 0x00 542f reserved area(104 bytes) 0x00 5430 ri reserved area (1 byte) 0x00 0x00 5431 ri_icr1 ri timer input capture routing register 1 0x00 0x00 5432 ri_icr2 ri timer input capture routing register 2 0x00 0x00 5433 ri_ioir1 ri i/o input register 1 0xxx 0x00 5434 ri_ioir2 ri i/o input register 2 0xxx 0x00 5435 ri_ioir3 ri i/o input register 3 0xxx 0x00 5436 ri_iocmr1 ri i/o control mode register 1 0x00 0x00 5437 ri_iocmr2 ri i/o control mode register 2 0x00 0x00 5438 ri_iocmr3 ri i/o control mode register 3 0x00 0x00 5439 ri_iosr1 ri i/o switch register 1 0x00 0x00 543a ri_iosr2 ri i/o switch register 2 0x00 0x00 543b ri_iosr3 ri i/o switch register 3 0x00 0x00 543c ri_iogcr ri i/o group control register 0xff 0x00 543d ri_ascr1 analog switch register 1 0x00 0x00 543e ri_ascr2 ri analog switch register 2 0x00 0x00 543f ri_rcr ri resist or control register 0x00 0x00 5440 to 0x00 544f reserved area (16 bytes) 0x00 5450 ri ri_cr ri i/o control register 0x00 0x00 5451 ri_maskr1 ri i/o mask register 1 0x00 0x00 5452 ri_maskr2 ri i/o mask register 2 0x00 0x00 5453 ri_maskr3 ri i/o mask register 3 0x00 0x00 5454 ri_maskr4 ri i/o mask register 4 0x00 0x00 5455 ri_ioir4 ri i/o input register 4 0xxx 0x00 5456 ri_iocmr4 ri i/o control mode register 4 0x00 0x00 5457 ri_iosr4 ri i/o switch register 4 0x00 1. these registers are not impacted by a sy stem reset. they are reset at power-on. table 7. general hardware register map (continued) address block register label register name reset status
memory and register map stm8l051f3 36/46 doc id 022985 rev 1 table 8. cpu/swim/debug module/interrupt controller registers address block register label register name reset status 0x00 7f00 cpu (1) a accumulator 0x00 0x00 7f01 pce program counter extended 0x00 0x00 7f02 pch program counter high 0x00 0x00 7f03 pcl program counter low 0x00 0x00 7f04 xh x index register high 0x00 0x00 7f05 xl x index register low 0x00 0x00 7f06 yh y index register high 0x00 0x00 7f07 yl y index register low 0x00 0x00 7f08 sph stack pointer high 0x03 0x00 7f09 spl stack pointer low 0xff 0x00 7f0a ccr condition code register 0x28 0x00 7f0b to 0x00 7f5f cpu reserved area (85 bytes) 0x00 7f60 cfg_gcr global c onfiguration register 0x00 0x00 7f70 itc-spr itc_spr1 interrupt software priority register 1 0xff 0x00 7f71 itc_spr2 interrupt software priority register 2 0xff 0x00 7f72 itc_spr3 interrupt software priority register 3 0xff 0x00 7f73 itc_spr4 interrupt software priority register 4 0xff 0x00 7f74 itc_spr5 interrupt software priority register 5 0xff 0x00 7f75 itc_spr6 interrupt software priority register 6 0xff 0x00 7f76 itc_spr7 interrupt software priority register 7 0xff 0x00 7f77 itc_spr8 interrupt software priority register 8 0xff 0x00 7f78 to 0x00 7f79 reserved area (2 bytes) 0x00 7f80 swim swim_csr swim c ontrol status register 0x00 0x00 7f81 to 0x00 7f8f reserved area (15 bytes) 0x00 7f90 dm dm_bk1re dm breakpoint 1 register extended byte 0xff 0x00 7f91 dm_bk1rh dm breakpoint 1 register high byte 0xff 0x00 7f92 dm_bk1rl dm breakpoint 1 register low byte 0xff 0x00 7f93 dm_bk2re dm breakpoint 2 register extended byte 0xff 0x00 7f94 dm_bk2rh dm breakpoint 2 register high byte 0xff 0x00 7f95 dm_bk2rl dm breakpoint 2 register low byte 0xff 0x00 7f96 dm_cr1 dm debug module control register 1 0x00
stm8l051f3 memory and register map doc id 022985 rev 1 37/46 0x00 7f97 dm dm_cr2 dm debug module control register 2 0x00 0x00 7f98 dm_csr1 dm debug module co ntrol/status register 1 0x10 0x00 7f99 dm_csr2 dm debug module co ntrol/status register 2 0x00 0x00 7f9a dm_enfctr dm enable function register 0xff 0x00 7f9b to 0x00 7f9f reserved area (5 bytes) 1. accessible by debug module only table 8. cpu/swim/debug module/interrupt controller registers (continued) address block register label register name reset status
interrupt vector mapping stm8l051f3 38/46 doc id 022985 rev 1 6 interrupt vector mapping table 9. interrupt mapping irq no. source block description wakeup from halt mode wakeup from active-halt mode wakeup from wait (wfi mode) wakeup from wait (wfe mode) (1) vector address reset reset yes yes yes yes 0x00 8000 trap software interrupt - - - - 0x00 8004 0tli (2) external top level interrupt - - - - 0x00 8008 1 flash flash end of programing/ write attempted to protected page interrupt - - yes yes 0x00 800c 2 dma1 0/1 dma1 channels 0/1 half transaction/transaction complete interrupt - - yes yes 0x00 8010 3 dma1 2/3 dma1 channels 2/3 half transaction/transaction complete interrupt - - yes yes 0x00 8014 4rtc rtc alarm a/wakeup/ tamper 1/tamper 2/tamper 3 yes yes yes yes 0x00 8018 5 pvd pvd interrupt yes yes yes yes 0x00 801c 6 extib external interrupt port b yes yes yes yes 0x00 8020 7 extid external interrupt port d yes yes yes yes 0x00 8024 8 exti0 external interrupt 0 yes yes yes yes 0x00 8028 9 exti1 external interrupt 1 yes yes yes yes 0x00 802c 10 exti2 external interrupt 2 yes yes yes yes 0x00 8030 11 exti3 external interrupt 3 yes yes yes yes 0x00 8034 12 exti4 external interrupt 4 yes yes yes yes 0x00 8038 13 exti5 external interrupt 5 yes yes yes yes 0x00 803c 14 exti6 external interrupt 6 yes yes yes yes 0x00 8040 15 exti7 external interrupt 7 yes yes yes yes 0x00 8044 16 reserved 0x00 8048 17 clk clk system clock switch/css interrupt - - yes yes 0x00 804c 18 adc1 acd1 end of conversion/ analog watchdog/ overrun interrupt yes yes yes yes 0x00 8050 19 tim2 tim2 update /overflow/trigger/break interrupt - - yes yes 0x00 8054
stm8l051f3 interrupt vector mapping doc id 022985 rev 1 39/46 20 tim2 tim2 capture/compare interrupt - - yes yes 0x00 8058 21 tim3 tim3 update /overflow/trigger/break interrupt - - yes yes 0x00 805c 22 tim3 tim3 capture/compare interrupt - - yes yes 0x00 8060 23 ri ri trigger interrupt - - yes - 0x00 8064 24 reserved 0x00 8068 25 tim4 tim4 update/overflow/ trigger interrupt - - yes yes 0x00 806c 26 spi1 spi1 tx buffer empty/ rx buffer not empty/ error/wakeup interrupt yes yes yes yes 0x00 8070 27 usart 1 usart1 transmit data register empty/ transmission complete interrupt - - yes yes 0x00 8074 28 usart 1 usart1 received data ready/overrun error/ idle line detected/parity error/global error interrupt - - yes yes 0x00 8078 29 i 2 c1 i 2 c1 interrupt (3) yes yes yes yes 0x00 807c 1. the low power wait mode is entered when executing a wf e instruction in low power run mode. in wfe mode, the interrupt is served if it has been previ ously enabled. after processi ng the interrupt, the processor goes back to wfe mode. when the interrupt is configured as a wakeup event, the cpu wakes up and resumes processing. 2. the tli interrupt is the logic or between tim2 overflow interrupt, and tim4 overflow interrupts. 3. the device is woken up from halt or active-halt mode only when the address received matches the interface address. table 9. interrupt mapping (continued) irq no. source block description wakeup from halt mode wakeup from active-halt mode wakeup from wait (wfi mode) wakeup from wait (wfe mode) (1) vector address
package characteristics stm8l051f3 40/46 doc id 022985 rev 1 7 package characteristics 7.1 ecopack in order to meet environmental requirements, st offers these devices in different grades of ecopack? packages, depending on their level of environmental compliance. ecopack? specifications, grade definitions and product status are available at: www.st.com. ecopack? is an st trademark.
stm8l051f3 package characteristics doc id 022985 rev 1 41/46 7.2 package mechanical data 7.2.1 20-lead thin shri nk small package (tssop20) 1. drawing is not to scale 2. dimensions are in millimeters figure 5. tssop20 20-lead thin shrink small package outline figure 6. tssop20 recommended footprint tssop20-m 1 20 cp c l e e1 d a2 a e b 10 11 a1 l1 bj table 10. tssop20 20-lead thin shrink small package, mechanical data dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 1.2 0.0472 a1 0.05 0.15 0.0020 0.0059 a2 0.8 1 1.05 0.0315 0.0394 0.0413 b 0.19 0.3 0.0075 0.0118 c 0.09 0.2 0.0035 0.0079 d 6.4 6.5 6.6 0.2520 0.2559 0.2598 e 6.2 6.4 6.6 0.2441 0.252 0.2598 e1 4.3 4.4 4.5 0.1693 0.1732 0.1772 e - 0.65 - 0.0256 - l 0.45 0.6 0.75 0.0177 0.0236 0.0295 l1 1 0.0394
package characteristics stm8l051f3 42/46 doc id 022985 rev 1 7.2.2 32-pin low profile quad flat package (lqfp32) figure 7. lqfp32 32-pin low profile quad flat package outline 5v_me l a1 k l1 c a a2 ccc c d d1 d3 e3 e1 e 16 17 24 25 b 32 1 pin 1 identification 8 9 table 11. lqfp32 32-pin low profile quad flat package, mechanical data dim. millimeters inches min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 0.200 0.0035 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 5.600 0.2205 e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 5.600 0.2205 e 0.800 0.0315 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394
stm8l051f3 package characteristics doc id 022985 rev 1 43/46 figure 8. lqfp32 recommended footprint 1. dimensions are in millimeters 9.40 7.70 0. 8 0 0.54 9.40 5v_fp
device ordering information stm8l051f3 44/46 doc id 022985 rev 1 8 device ordering information figure 9. low density value line stm8l05xxx ordering information scheme stm8 l 051 f 3 p 6 product class stm8 microcontroller pin count f = 20 pins package p = tssop example: sub-family type 051 = ultra low power family type l = low power temperature range 6 = ? 40 to 85 c for a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please contact the st sales office nearest to you. program memory size 3 = 8 kbytes
stm8l051f3 revision history doc id 022985 rev 1 45/46 9 revision history table 12. document revision history date revision changes 23-apr-2012 1 initial release.
stm8l051f3 46/46 doc id 022985 rev 1 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2012 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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